1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a technique for dealing with heavy metal pollution of a semiconductor device.
2. Description of the Related Art
In a typical semiconductor device, a deep n-type well (may be hereinafter referred to as a n-type well) is formed in a p-type semiconductor substrate, and a shallow p-type well (may be hereinafter referred to as a p-type well) is formed in the deep n-type well. Moreover, a MOS transistor is formed on the shallow p-type well. The MOS transistor has a n-type source/drain diffusion layer, a gate oxide film and a gate electrode.
Such a semiconductor device is manufactured through several processes. During the manufacturing processes, there is a possibility that the semiconductor device is polluted with heavy metal. If heavy metal ions move into a depletion layer around a p-n junction between the n-type source/drain diffusion layer and the shallow p-type well due to the heavy metal pollution, a p-n junction leakage current through the p-n junction increases. The increase in the p-n junction leakage current causes circuit malfunction such as deterioration of data retention characteristic of a DRAM, increase in a standby current in an SRAM and the like, which decreases the reliability of the semiconductor device. It is therefore desirable to provide a technique that can eliminate heavy metals from around the p-n junction.
Moreover, a characteristic inspection is usually carried out for plural times during the above-mentioned processes of manufacturing the semiconductor device. For example, a characteristic inspection is performed in a wafer state, and another characteristic is further performed after a packaging process. If the heavy metal pollution occurs prior to a characteristic inspection process in the wafer state, the yield at the characteristic inspection process in the wafer state is decreased. Moreover, if the heavy metal pollution occurs during a wafer back-side grinding process or the packaging process, a non-defective product may become a defective product which is found at the characteristic inspection after the packaging process is completed. That is to say, the number of defective products increases and the yield decreases at every characteristic inspection process.
It is therefore desirable to improve the yield at each characteristic inspection process and thereby to improve the yield as a whole.
Japanese Laid-Open Patent Application JP-P2005-277116 discloses a semiconductor device provided with a gettering layer. The gettering layer is formed by implanting impurities into a chip back-side after a semiconductor chip is produced.